1. Technical Field of the Invention
The present invention relates to timing generator circuits used in TG (timing generator) sections of IC testers and the like, and more specifically to timing generator circuits which output rate signal pulses of undefined periods after delaying them by the intervals of clock periods assigned by delay assignment data which are provided in synchronization.
2. Background Art
In IC tests due to IC testers, constant measurement sequences are carried out at defined timings. For example, IC function tests are basically performed by the repetition of the following procedure.
a. Test patterns for the function test are read one at a time from a memory at timings which are defined by a program (a measurement program which determines the measurement procedure for the relevant IC). PA0 b. Patterns corresponding to the IC input terminals are selected from among the binary data of "1"'s and "0"'s forming the readout pattern, and a voltage waveform corresponding to these "1"'s and "0"'s is supplied to each input terminal of the IC at a timing determined by the program. PA0 c. As a result, response waveforms obtained from each output terminal of the IC are sampled at timings determined by the program, and the results are collated with the test patterns in order to judge whether or not the IC is functioning normally.
In order to properly perform these types of function tests, timing control must be performed so that the procedure can be performed with the determined timings.
Additionally, depending on the IC which is undergoing the test, instead of supplying the binary data forming a pattern immediately as an input waveform to the IC, there may be cases wherein a voltage waveform corresponding to the binary data is supplied to the IC after a time lag of a desired interval, or wherein a multiplexed clock signal is generated in accordance with the binary data and supplied to the IC. These types of tests require more complex timing control schemes.
As means for performing this type of timing control, various types of timing generator circuits are provided in IC testers. FIG. 5 shows an example of the structure of such a timing generator circuit. This timing generator circuit operates in synchronization with a clock signal .phi..sub.0 having a constant frequency f.sub.0, and delays rate signal pulses supplied from other circuitry inside the tester by a time interval assigned at a resolution of 1/f.sub.0, then outputs them as timing signals. Additionally, in this example, the structure is such as to be capable of delaying the rate signal pulses by 4 rates (wherein 1 rate is the interval between the rate signal pulses).
As shown in FIG. 5, this timing generator circuit comprises a demultiplexer 11, a counter section 12 and a multiplexer 13.
The demultiplexer 11 is a circuit which quadruple-interleaves delay assignment data D.sub.0 and a rate pulse signal T.sub.0 supplied from a control section (IC tester control system) which is not shown in the drawing, then outputs the results from first through fourth output terminals. That is, if this demultiplexer 11 outputs delay assignment data D.sub.0 and a rate signal pulse T.sub.0 supplied at a certain time from the first output terminal, the next delay assignment data D.sub.0 and rate signal pulse T.sub.0 are outputted from the second output terminal, and the next delay assignment data D.sub.0 and rate signal pulse T.sub.0 are outputted from the third output terminal, so as to output the delay assignment data D.sub.0 and rate signal pulse T.sub.0 while sequentially switching the output terminal.
The counter section 12 has four internal down-counters 12.sub.A .about.12.sub.D. These down-counters 12.sub.A .about.12.sub.D have mutually independent load input terminals LD and data input terminals DATA. The rate signal pulse T.sub.0 and delay assignment data D.sub.0 quadruple-interleaved by the demultiplexer 11 are respectively supplied to the load input terminal LD and the data input terminal DATA of each down-counter. Additionally, the down-counters 12.sub.A .about.12.sub.D each count down in accordance with a clock signal .phi..sub.0 of frequency f.sub.0, and output a pulse when the count value reaches "0". The multiplexer 13 multiplexes the four pulses obtained from these down-counters 12.sub.A .about.12.sub.D, then outputs the result as timing signal T.sub.OUT.
As explained above, the demultiplexer 11 quadruple-interleaves and outputs rate signal pulses T.sub.0 and delay assignment data D.sub.0. Therefore, when considering the down-counters 12.sub.A .about.12.sub.D, each down-counter is supplied with a rate signal pulse T.sub.0 and delay assignment data D.sub.0 for each four rate signal pulses that arrive from the demultiplexer 11, and the delay assignment data D.sub.0 is assigned as the initial count value. Each down-counter counts down from this initial value with the clock signal .phi..sub.0 and generates a pulse when the count value becomes "0". That is, the down-counters 12.sub.A .about.12.sub.D are able to count over three intervals of the rate signal pulses, i.e. over four rates; therefore, the rate signal pulses can be delayed by four rates.
FIG. 6 is a time chart showing the operations of the timing generator circuit. Hereinbelow, the operations of the timing generator circuit will be explained with reference to the diagram. In this diagram, N.sub.1 .about.N.sub.4 are the count values of the respective down-counters 12.sub.A .about.12.sub.D, T.sub.1 .about.T.sub.4 are the pulses outputted from the respective down-counters 12.sub.A .about.12.sub.D, and T.sub.OUT is a timing signal outputted from the multiplexer 13.
First, a rate signal pulse T.sub.0 (t.sub.1) and delay assignment data D.sub.0 (d.sub.1) are supplied, then inputted to the down-counter 12.sub.B via the demultiplexer 11. In this example, a "7" which orders a "delay of 7 clock minutes" is supplied as the delay assignment data D.sub.0 (d.sub.1). Therefore, a "7" is assigned to the down-counter 12.sub.B, and a countdown is started with this "7" as the initial value in accordance with the clock signal .phi..sub.0. In a similar manner, when the next rate signal pulse T.sub.0 (t.sub.2) and delay assignment data D.sub.0 (d.sub.2) (="5") are supplied, a "5" is assigned to the down-counter 12.sub.C via the demultiplexer 11. At this time, the count value N.sub.2 of the down-counter 12.sub.B is "4", and a parallel countdown is performed in accordance with the clock signal .phi..sub.0 by the down-counters 12.sub.B and 12.sub.C.
When the next rate signal pulse T.sub.0 (t.sub.3) and delay assignment data D.sub.0 (d.sub.3) (="5") are supplied, a "5" is assigned to the down-counter 12.sub.D via the demultiplexer 11. At this time, the count value N.sub.2 of the down-counter 12.sub.B is "3", the count value N.sub.3 of the down-counter 12.sub.C is "4", and a parallel countdown is performed in accordance with the clock signal .phi..sub.0 by the down-counters 12.sub.B and 12.sub.C and 12.sub.D.
When the next rate signal pulse T.sub.0 (t.sub.4) and delay assignment data D.sub.0 (d.sub.4) (="4") are supplied, a "4" is assigned to the down-counter 12.sub.A via the demultiplexer 11. At this time, the count values of the down-counters 12.sub.B, 12.sub.C and 12.sub.D are "1", "2" and "3", and a parallel countdown is performed by all of the down-counters. When the next clock signal .phi..sub.0 is supplied, the value at the down-counter 12.sub.B becomes "0", so that the down-counter 12.sub.B generates a pulse T.sub.2 and stops the countdown. Thereafter, the count values of the down-counters 12.sub.C, 12.sub.D and 12.sub.A sequentially become "0", so that each down-counter sequentially outputs a pulse T.sub.3, T.sub.4 and T.sub.1, then stops the count. These pulses are multiplexed by the multiplexer 13 and supplied to the circuits inside the IC tester as timing signal T.sub.OUT so as to be used for timing control in the procedure for creating voltage waveforms to be supplied to the IC being tested.
In order to form IC testers which are capable of high-precision measurements, the resolution of the generation timing of the timing signals must be increased. Furthermore, in order to increase the resolution, the frequency f.sub.0 of the clock signal .phi..sub.0 supplied to the counter section 12 must be increased. However, the conventional timing generator circuit described above has a structure wherein n (n=4 in FIG. 5) down-counters are connected in parallel inside the counter section 12, so as to require a large amount of hardware which operates at high speeds of frequency f.sub.0, thereby resulting in considerable power consumption and a high cost.